The JEDEC Solid State Technology Association has released a preliminary draft specification for DDR6 SDRAM, targeting data transfer rates of 12800MT/s and presenting greater challenges for signal integrity design.
The newly released ANSYS 2026 R2 version integrates AI-driven simulation parameter optimization, automatically searching for optimal mesh settings and solver parameters.
PCI-SIG announces the official freeze of the PCIe Gen6 Physical Layer specification, which uses PAM4 modulation at 64GT/s rates, presenting new challenges for channel simulation and equalization design.
IEEE has initiated 800Gb/s Ethernet standardization efforts targeting a single-channel rate of 200Gbps, introducing new requirements for high-speed SerDes design.
Cadence releases a power integrity analysis platform with an integrated AI engine, enabling full-chip PDN simulation and optimization.